Modular 6502 SBC with emulated CPU

My test setup – bottom: ATMega16 with a 32k SRAM, 64k I²C EEPROM, top: 2*74HC573, 6532, LCD …and yes, it works on a breadboard.

Overview

The minimum system consists of an ATMega16, an SRAM IC and some components to provide a clock source and an RS232 interface. Non volatile program storage can be added in an I²C EEPROM connected through a bilateral switch. Examples in the source code showcase, how parallel IO can be added from simple latches to 65xx IO ICs.

 

The emulation provides:

·          some of the ATMega’s internal IO capabilities

o   RS232

o   I²C/TWI

o   SPI

o   Timers

o   Interrupt pins as IRQ and NMI inputs

·          proper sequencing of tags for parallel IO devices

o   glue logic replaced by emulation IO modules and simple registers

·          a debugger & monitor outside of the emulated CPUs code space

o   alter and display registers and memory

o   program control – start, stop, single step & breakpoint

o   trap undefined opcodes or STP instruction

·         loading or booting code images to RAM from

o    RS232 (monitor console)

o    serial I²C or SPI EEPROM

 

The achievable 6502 equivalent clock speed is approximately 2 MHz at 16 MHz ATMega clock.

 

In order to combine the required IO blocks for your own SBC design, some AVR assembler knowledge is required. The emulator source code contains extensive comments about configurable items and the usage of emulated registers in the IO page.

Project status, planned additions

Previous:

Version 0.8 is the initial release. It has passed all tests of the emulated opcodes, IO loopback to I²C EEPROM, 74HC573 latches, a 6532 RIOT and a HD44780 compatible LCD.

 

Version 0.81 – Added binary load/save/autoload support for applications. Added optional software flow control to RS232 receive buffer and tested with PuTTY and Tera Term. Modified EhBASIC for use with the emulator. Condensed all configurable items into a single include file. Added timer 1 access. Tested and improved interrupts.

 

Version 0.82 – Added optional 65C02 opcodes emulation.

 

Version 0.83 – Added breakpoint capability. Added SPI support. Added virtual but interruptible DMA for both I²C & SPI. Added documentation about customizing the AVR source and using the IO‑registers. Updated hardware and debugger documentation. Merged all documentation into a single document.

Major update:  the configuration include must be replaced with version 0.83.

 

Version 0.83a – Modified atomic mode (irq_dis_real defined) to accept single step and NMI.

Current:

Version 0.83b – Bug fix release. The last version fitting the ATMEGA16

Add:

·         enable a special SD-card partition to replace the serial EEPROM

·         extended memory swap using DMA – access to RAM > 64k (poor man’s MMU)

·         optional secondary AVR as independent IO processor

Documentation

6502 Emu reference manual update 17-aug-2014

6502 Emu instruction cycle times update 17-aug-2014

65C02 Emu instruction cycle times update 17-aug-2014

Downloads

6502 Emu source code for the ATMega16 version 0.83b, 24-jan-2015

6502 functional tests update 17-aug-2014

EhBASIC for use with Version 0.83x of the emulator, update 17-may-2014

6502 assembler IO examples

Links

Me on GitHub – the emulator and test source is also available on GitHub.

6502.org: The 6502 Microprocessor Resource – lots of information and an active forum

Atmel AVR Microcontrollers – documentation and IDE for the ATMega16 & ATMega32

Frank's Cross Assemblers – AS65, the assembler that I use

PSPad code editor – set up as a frontend to AS65

PuTTY – although it does much more, I use it as a serial terminal emulation

Tera Term – can be used as an alternative